dc.contributor.advisor | Bhuian, Dr. Mohammed Belal Hossain | |
dc.contributor.advisor | Saha, Atanu Kumar | |
dc.contributor.author | Haque, Tausif Omar | |
dc.contributor.author | Shifain, Joyoti | |
dc.contributor.author | Mallick, Protim | |
dc.contributor.author | Islam, Md. Rizwanul | |
dc.date.accessioned | 2015-09-01T07:10:28Z | |
dc.date.available | 2015-09-01T07:10:28Z | |
dc.date.copyright | 2015 | |
dc.date.issued | 2015-07 | |
dc.identifier.other | ID 11221030 | |
dc.identifier.other | ID 11221004 | |
dc.identifier.other | ID 11221025 | |
dc.identifier.other | ID 11221020 | |
dc.identifier.uri | http://hdl.handle.net/10361/4330 | |
dc.description | This thesis report is submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Electronic Engineering, 2015. | en_US |
dc.description | Cataloged from PDF version of thesis report. | |
dc.description | Includes bibliographical references (page 47-48). | |
dc.description.abstract | QWFETs with non-planar, multigate structures are known to provide higher electrostatistics
than their conventional planar counterparts. Due to this desirable feature of the non-planar,
multigate architecture, the electronics community is leaning towards transistors having gates
wrapped around the channel for higher scalability and performance.
In this work, 2-D Schrodinger-Poisson coupled simulations of non-planar, multigate InGaAs
QWFETs were carried out using an in-house simulator to study the performance of the devices
based on the C-V characteristics. The simulator was carefully benchmarked to evaluate its
accuracy before carrying out the simulations. Two InGaAs QWFETs with InAlAs spacer layers
were simulated. The first device had a plain InAlAs spacer layer and the second device
contained a Si δ-doped layer between InAlAs spacer layer. The simulation results showed that
the device with the plain InAlAs spacer layer had a threshold voltage of 0.3V and C-V
characteristics similar to that of a device with an InP spacer layer which was used for
benchmarking. The second device which contained a thin Si δ-doped layer within the InAlAs
spacer layer was simulated next. From the simulation results, it was seen that the device had a
threshold voltage of 0.2V and an effective improvement in C-V characteristics was also
observed compared to the device with plain InAlAs layer. | en_US |
dc.description.statementofresponsibility | Tausif Omar Haque | |
dc.description.statementofresponsibility | Joyoti Shifain | |
dc.description.statementofresponsibility | Protim Mallick | |
dc.description.statementofresponsibility | Md. Rizwanul Islam | |
dc.format.extent | 48 pages | |
dc.language.iso | en | en_US |
dc.publisher | BRAC University | en_US |
dc.rights | BRAC University thesis are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. | |
dc.subject | Electrical and electronic engineering | en_US |
dc.subject | Simulation | en_US |
dc.title | Simulation based study of non-planar multigate indium gallium arsenide quantum well field effect transistors | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | Department of Electrical and Electronic Engineering, BRAC University | |
dc.description.degree | B. Electrical and Electronic Engineering | |