Hardware architecture design of face recognition system based on FPGA

Abstract

A novel hardware architecture for face-recognition system has been proposed in this paper. In order to make the system cost effective a simple yet efficient algorithm of face-recognition system has been used. We have designed, implemented and verified the algorithm in a cyclone III Field Programmable Gate Array (FPGA) chip. Altera DE0 development board which contains a cyclone III chip on it has been used for debugging purpose. We have also ensured for low power consumption such that the chip could be used universally in a wide range of security systems. To develop a simple yet efficient face recognition algorithm (such as PCA, FFT etc.) on digital hardware, we have researched on various face recognition algorithms using MATLAB codes and studied their detection efficiency under various posture and background and also the complexity of the algorithm. To save hardware resource and at the same time to obtain an acceptable level of recognition we have chosen to use Fast Fourier Transform (FFT).