Development of custom RISC-V central processing unit (CPU) with open-source Google + SkyWater 130 nm

Abstract

The chip design industry relies heavily on secretive methodologies and designs. A significant gap exists between commercial design environment and open-source environment. Although a range of open-source CAD tools has been developed to address aspects such as system design, logic synthesis, place-and-route, test insertion, and verification, there is no established toolchain for open-source library characterization. This thesis aims to develop that toolchain for open-source library characterization and develop a custom standard cell library based on Google + SkyWater 130nm technology. To further verify the toolchain and libraries, a RISC- V CPU is designed with the same library using established open-source Place and Route tools and simulated for result verification. Therefore, this work aims to tackle issues related to open-source chip design while diving deep into open-source tools to design a RISC V CPU. To achieve this, the gaps which remain between the ASIC design done with commercial design tools and open-source tools are addressed and bridged.