Simulation based study of non-planar multigate indium gallium arsenide quantum well field effect transistors

Abstract

QWFETs with non-planar, multigate structures are known to provide higher electrostatistics than their conventional planar counterparts. Due to this desirable feature of the non-planar, multigate architecture, the electronics community is leaning towards transistors having gates wrapped around the channel for higher scalability and performance. In this work, 2-D Schrodinger-Poisson coupled simulations of non-planar, multigate InGaAs QWFETs were carried out using an in-house simulator to study the performance of the devices based on the C-V characteristics. The simulator was carefully benchmarked to evaluate its accuracy before carrying out the simulations. Two InGaAs QWFETs with InAlAs spacer layers were simulated. The first device had a plain InAlAs spacer layer and the second device contained a Si δ-doped layer between InAlAs spacer layer. The simulation results showed that the device with the plain InAlAs spacer layer had a threshold voltage of 0.3V and C-V characteristics similar to that of a device with an InP spacer layer which was used for benchmarking. The second device which contained a thin Si δ-doped layer within the InAlAs spacer layer was simulated next. From the simulation results, it was seen that the device had a threshold voltage of 0.2V and an effective improvement in C-V characteristics was also observed compared to the device with plain InAlAs layer.