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Novel approaches to low leakage and area efficient VLSI Design

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dc.contributor.author Izma, Tajrian
dc.contributor.author Barua, Parag
dc.contributor.author Rahman, Md. Rejaur
dc.contributor.author Sengupta, Prianka
dc.date.accessioned 2011-11-15T07:04:43Z
dc.date.available 2011-11-15T07:04:43Z
dc.date.issued 2011-08
dc.identifier.other ID 09221088
dc.identifier.other ID 09221082
dc.identifier.other ID 09221157
dc.identifier.other ID 09221092
dc.identifier.uri http://hdl.handle.net/10361/1469
dc.description This thesis is submitted in a partial fulfillment of the requirement for the degree of Bachelor of Science in Electrical and Electronic Engineering. en_US
dc.description.abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Thinner gate oxides have led to an increase in gate leakage current. Today leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. According to the International Technology Roadmap for Semiconductors (ITRS) [1], leakage power dissipation may eventually dominate total power consumption as technology feature sizes shrink. While there are several process technology and circuit-level solutions to reduce leakage in processors, we propose novel approaches for reducing both leakage and dynamic power with minimum possible area and delay trade off. en_US
dc.language.iso en en_US
dc.publisher Department of Electrical and Electronic Engineering en_US
dc.title Novel approaches to low leakage and area efficient VLSI Design en_US
dc.type Thesis en_US


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