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Novel approaches to low leakage and area efficient VLSI Design

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dc.contributor.advisor Islam, Md. Shafiqul Izma, Tajrian Barua, Parag Rahman, Md. Rejaur Sengupta, Prianka 2011-11-15T07:04:43Z 2011-11-15T07:04:43Z 2011 2011-08
dc.identifier.other ID 09221088
dc.identifier.other ID 09221082
dc.identifier.other ID 09221157
dc.identifier.other ID 09221092
dc.description his thesis report is submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Electronic Engineering, 2011. en_US
dc.description Cataloged from PDF version of thesis report.
dc.description Includes bibliographical references (page 51-53).
dc.description.abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Thinner gate oxides have led to an increase in gate leakage current. Today leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. According to the International Technology Roadmap for Semiconductors (ITRS) [1], leakage power dissipation may eventually dominate total power consumption as technology feature sizes shrink. While there are several process technology and circuit-level solutions to reduce leakage in processors, we propose novel approaches for reducing both leakage and dynamic power with minimum possible area and delay trade off. en_US
dc.description.statementofresponsibility Tajrian Izma
dc.description.statementofresponsibility Parag Barua
dc.description.statementofresponsibility Md. Rejaur Rahman
dc.description.statementofresponsibility Prianka Sengupta
dc.format.extent 65 pages
dc.language.iso en en_US
dc.publisher BRAC University en_US
dc.rights BRAC University thesis are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission.
dc.subject Electrical and electronic engineering
dc.title Novel approaches to low leakage and area efficient VLSI Design en_US
dc.type Thesis en_US
dc.contributor.department Department of Electrical and Electronic Engineering, BRAC University B. Electrical and Electronic Engineering

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