Rahman, TouhidurHossain, MG SorwarHarun-Ur-Rashid, A. B. M.Rahman, Md. MosaddequrRahman, Md. Shyeem2026-01-132026-01-1320252025-09ID 21161006http://hdl.handle.net/10361/27428Cataloged from PDF version of thesis.Includes bibliographical references (pages 101-107).This thesis is submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Electronic Engineering, 2025.The chip design industry relies heavily on secretive methodologies and designs. A significant gap exists between commercial design environment and open-source environment. Although a range of open-source CAD tools has been developed to address aspects such as system design, logic synthesis, place-and-route, test insertion, and verification, there is no established toolchain for open-source library characterization. This thesis aims to develop that toolchain for open-source library characterization and develop a custom standard cell library based on Google + SkyWater 130nm technology. To further verify the toolchain and libraries, a RISC- V CPU is designed with the same library using established open-source Place and Route tools and simulated for result verification. Therefore, this work aims to tackle issues related to open-source chip design while diving deep into open-source tools to design a RISC V CPU. To achieve this, the gaps which remain between the ASIC design done with commercial design tools and open-source tools are addressed and bridged.102 pagesenBRAC University theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission.Open source vlsi toolLibrary characterizationPVT variationGoogle + skywaterAutomatic placement and routeRISC-VCPU designOpen source software.Electrical engineering.RISC microprocessors.Microprocessors--Design and construction.Thesis