Duper scalar processor : the hardware approach to instruction level parallelism

Abstract

Multi-core processors are being widely used nowadays and the numbers of cores are increasing in the commercial arena with great speed with the gigahertz race between the two stalwarts, Intel and AMD. Usually the cores are symmetric, which means that all the cores are functionally identical. This paper proposes an architecture that brings in a new dimension to instruction level parallelism. The operating system in today’s machines does all the decision making as to how the instructions in a task can be parallelized by deciding which task gets assigned to which core. The hardware support for exploiting instruction level parallelism is very small and has very little decision making power. Most recently dynamic scheduling of the instructions paved the pathway for major hardware changes and hence the decision making power shared. But the problem still persists. The operating has no direct help from the hardware and has to do most of the work at software level and hence the operating system has to be modified as the number of cores increase and the type of cores change. So a hardware support is a necessity in order to keep the operating system unchanged so that it doesn’t have to worry about the cores. This hardware support greatly simplifies the design of the OS, which is trying to make the maximum benefits of multi-core processors without needing changes as the number of cores change.