An advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS

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bracu.type.groupResearch Publications
datacite.rightsMetadata Only
dc.contributor.authorShahriar, Md. Sumon
dc.contributor.authorMustafa A.R.
dc.contributor.authorAhmed C.F.
dc.contributor.authorFerdaus A.A.
dc.contributor.authorZaheduzzaman A.N.M.
dc.contributor.authorAnwar S.
dc.contributor.authorBabu H.M.H.
dc.contributor.departmentDepartment of Computer Science and Engineering
dc.date.accessioned2026-08-18T05:41:21Z
dc.date.available2026-08-18T05:41:21Z
dc.date.issued2005-12-01
dc.description.abstractWe proposed an advanced minimization method for multiple valued multiple output functions in this paper. We extracted the shared sub functions with a proposed heuristic method to pair the functions. New minimization approach for multiple valued functions has also been proposed where we used Kleenean Coefficients and we used LUT to reduce the complexity as well. Our minimization method reduces the number of implicants significantly. The realization of the minimized circuits has also been shown using current mode CMOS.
dc.description.versionPublished
dc.format.extent122-126
dc.identifier.citationM. S. Shahriar et al., "An advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS," 8th Euromicro Conference on Digital System Design (DSD'05), Porto, Portugal, 2005, pp. 122-126, doi: 10.1109/DSD.2005.13.
dc.identifier.doi10.1109/DSD.2005.13
dc.identifier.issn0769524338, 9780769524337
dc.identifier.issn9780769524337
dc.identifier.other2-s2.0-33845327484
dc.identifier.urihttps://hdl.handle.net/10361/29238
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.hasversion10.1109/DSD.2005.13
dc.relation.ispartofProceedings Dsd 2005 8th Euromicro Conference on Digital System Design Architectures Methods and Tools
dc.relation.ispartofseriesProceedings Dsd 2005 8th Euromicro Conference on Digital System Design Architectures Methods and Tools
dc.relation.urihttps://ieeexplore.ieee.org/document/1559788
dc.subjectCMOS logic circuits
dc.subjectTable lookup
dc.subjectMinimization methods
dc.subjectProgrammable logic arrays
dc.subjectDH-HEMTs
dc.subjectAsia
dc.subjectLogic design
dc.subjectCost function
dc.subjectSemiconductor devices
dc.subjectInput variables
dc.subject.lcshIntegrated circuits--Design and construction.
dc.titleAn advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS
dc.typeConference Proceeding
oaire.citation.volume2005
person.affiliation.nameUniversity of Dhaka
person.affiliation.nameUniversity of Dhaka
person.affiliation.nameUniversity of Dhaka
person.affiliation.nameUniversity of Dhaka
person.affiliation.nameStamford University Bangladesh
person.affiliation.nameUniversity of Dhaka
person.affiliation.nameUniversity of Dhaka
person.identifier.scopus-author-id57087371100
person.identifier.scopus-author-id15127844500
person.identifier.scopus-author-id24337639400
person.identifier.scopus-author-id15126436200
person.identifier.scopus-author-id15128218000
person.identifier.scopus-author-id15126690800
person.identifier.scopus-author-id55665833400

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