A comprehensive 9T standard cell framework for bridging VLSI education and industry practices using GPDK045

Abstract

A novel framework fo VLSI education is presented, addressing the widening gap between academic instruction and industry practices. At its core lies a 9-track standard cell library, designed using GPDK045 in Cadence Virtuoso with a 0.395-micron constant poly pitch. The approach integrates industry-standard verification processes, including DRC and LVS checks, alongside comprehensive evaluation methodologies for delay and transition analysis. Advanced features such as abutment testing and automated abstract generation are incorporated. The resulting holistic methodology provides students with hands-on experience using cutting-edge tools, preparing them for modern semiconductor industry challenges. This paper details the implementation and discusses the framework's potential impact on VLSI education and workforce readiness.