Show simple item record

dc.contributor.authorMondol, Raktim Kumar
dc.contributor.authorKhan, Muhammadimran
dc.contributor.authorMahbubul, Hye, A. K.
dc.contributor.authorHassan, Asif S.
dc.date.accessioned2016-11-27T06:53:34Z
dc.date.available2016-11-27T06:53:34Z
dc.date.issued2015
dc.identifier.citationMondol, R. K., Khan, M. I., Mahbubul Hye, A. K., & Hassan, A. (2015). Hardware architecture design of face recognition system based on FPGA. Paper presented at the ICIIECS 2015 - 2015 IEEE International Conference on Innovations in Information, Embedded and Communication Systems, doi:10.1109/ICIIECS.2015.7193228en_US
dc.identifier.isbn978-147996818-3
dc.identifier.urihttp://hdl.handle.net/10361/6978
dc.descriptionThis conference paper was presented in the 2nd IEEE International Conference on Innovations in Information, Embedded and Communication Systems, ICIIECS 2015; Karpagam College of EngineeringCoimbatore; India; 19 March 2015 through 20 March 2015 [© 2015 Institute of Electrical and Electronics Engineers Inc.] The conference paper's definite version is available at: http://10.1109/ICIIECS.2015.7193228en_US
dc.description.abstractA novel hardware architecture for face-recognition system has been proposed in this paper. In order to make the system cost effective a simple yet efficient algorithm of face-recognition system has been used. We have designed, implemented and verified the algorithm in a cyclone III Field Programmable Gate Array (FPGA) chip. Altera DE0 development board which contains a cyclone III chip on it has been used for debugging purpose. We have also ensured for low power consumption such that the chip could be used universally in a wide range of security systems. To develop a simple yet efficient face recognition algorithm (such as PCA, FFT etc.) on digital hardware, we have researched on various face recognition algorithms using MATLAB codes and studied their detection efficiency under various posture and background and also the complexity of the algorithm. To save hardware resource and at the same time to obtain an acceptable level of recognition we have chosen to use Fast Fourier Transform (FFT).en_US
dc.language.isoenen_US
dc.publisher© 2015 Institute of Electrical and Electronics Engineers Inc.en_US
dc.relation.urihttp://ieeexplore.ieee.org/document/7193228/
dc.subjectDSP Algorithmen_US
dc.subjectFace Recognitionen_US
dc.subjectFFTen_US
dc.subjectField Programmable Gate Array (FPGA)en_US
dc.subjectImage Processingen_US
dc.subjectPCAen_US
dc.subjectVLSIen_US
dc.titleHardware architecture design of face recognition system based on FPGAen_US
dc.typeConference Paperen_US
dc.description.versionPublished
dc.contributor.departmentDepartment of Electrical and Electronic Engineering
dc.identifier.doi10.1109/ICIIECS.2015.7193228


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record