dc.contributor.author | Sadekin, Intekhab | |
dc.date.accessioned | 2010-10-07T09:32:09Z | |
dc.date.available | 2010-10-07T09:32:09Z | |
dc.date.copyright | 2007 | |
dc.date.issued | 2007-08 | |
dc.identifier.other | ID 05341002 | |
dc.identifier.uri | http://hdl.handle.net/10361/381 | |
dc.description | This thesis report is submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering, 2007. | en_US |
dc.description | Cataloged from PDF version of thesis report. | |
dc.description | Includes bibliographical references (page 63). | |
dc.description.abstract | Multi-core processors are being widely used nowadays and the numbers of cores
are increasing in the commercial arena with great speed with the gigahertz race
between the two stalwarts, Intel and AMD. Usually the cores are symmetric,
which means that all the cores are functionally identical.
This paper proposes an architecture that brings in a new dimension to instruction
level parallelism. The operating system in today’s machines does all the decision
making as to how the instructions in a task can be parallelized by deciding which
task gets assigned to which core. The hardware support for exploiting instruction
level parallelism is very small and has very little decision making power. Most
recently dynamic scheduling of the instructions paved the pathway for major
hardware changes and hence the decision making power shared. But the
problem still persists. The operating has no direct help from the hardware and
has to do most of the work at software level and hence the operating system has
to be modified as the number of cores increase and the type of cores change. So
a hardware support is a necessity in order to keep the operating system
unchanged so that it doesn’t have to worry about the cores.
This hardware support greatly simplifies the design of the OS, which is trying to
make the maximum benefits of multi-core processors without needing changes
as the number of cores change. | en_US |
dc.description.statementofresponsibility | Intekhab Sadekin | |
dc.format.extent | 63 pages | |
dc.language.iso | en | |
dc.publisher | BRAC University | en_US |
dc.rights | BRAC University thesis are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. | |
dc.subject | Computer science and engineering | |
dc.title | Duper scalar processor : the hardware approach to instruction level parallelism | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | Department of Computer Science and Engineering, BRAC University | |
dc.description.degree | B. Computer Science and Engineering | |