Design and VLSI implementation of high performance face recognition system
MetadataShow full item record
In this paper, we have proposed a novel hardware architecture for face-recognition system. In order to make the system cost effective we have used a simple yet efficient algorithm of face-recognition system. We have designed, implemented and verified the algorithm in a cyclone III Field Programmable Gate Array (FPGA) chip. Altera DE0 development board which contains a cyclone III chip on it have been used for debugging purpose. We have also ensured for low power consumption such that the chip could be used universally in a wide range of security systems. To develop a simple yet efficient face recognition algorithm (such as PCA, FFT etc.) on digital hardware, we have researched on various face recognition algorithms using Matlab codes and studied their detection efficiency under various posture and background and also the complexity of the algorithm. To save hardware resource and at the same time to obtain an acceptable level of recognition we have chosen to use Fast Fourier Transform. The search database is developed by taking pictures of BRAC University students in various background and postures and used them to evaluate the developed face recognition system. Images were captured using TRDB_D5M camera module and digital data from the camera was transferred to the SDRAM of the DE0 board using GPIO interface. A NIOS2 microprocessor was synthesized in the cyclone III chip which controlled the total recognition system and the communication between the FFT core, SDRAM and On-chip memory. The performance of the hardware is now under evaluation.