Abstract:
In this paper, device manufacturing as a whole has been explored to discover whether graphene could be a
prospective material for device fabrication or not. As a part of this exploration, the current device manufacturing
process and its limitations have been examined. According to Moore’s law, the number of transistors per
square inch on integrated circuits had doubled ever year since the invention of integrated circuit and is
expected to continue so for future. To sustain Moore’s law in semiconductor manufacturing industry, the
size of devices have to be smaller and smaller in the near future. The use of Si in device manufacturing is
going through its fundamental limitations including scaling limitation and mobility issue. Research has
shown that when Si is cut into very narrow ribbons or layers, the mobility decreases significantly and at the same
time silicon’s characteristics vary considerably with the changes in temperature. Thus at this era of smaller and
smarter devices, the researchers have started their venture of searching for an alternative for Si in nanoelectronics. If not an alternative then at least as a prospective material for future nanoelectronics, graphene has attracted the attention of many due to its superior mobility, excellent thermal conductivity, availability and low cost. Graphene being regarded as a “miracle material” has proved itself to be a probable replacement for Si in nano-scale device manufacturing as being cut into nano-meter size layers, the mobility remains high even at room temperature. An absense of a proper bandgap in graphene making it impossible to turn the conduction off in graphene device, puts graphene-based device manufacturing under scrutiny.The research does not stop here as graphene has already exhibited its other outstanding characteristics which still open up the chances for graphene’s use as an epitaxial layer on other semiconducting substrates in order to fabricate devices. Epitaxial layer on SiC/SiO2 substrates is one of these prospective methods. However the limitations given, the approach towards fabricating all-graphene devices is on its way and thus the need of engineering a bandgap in graphene arises urgently. The matter of anticipation is that some prospective methods have been proposed by a lot of researchers around the world to obtain or induce a bandgap in graphene. Some of the approaches include Scanning Tunnelling Probe Microscope (STM) lithography, using Graphene Oxide (GO) sheets to bridge the gap between two epitaxial graphene layers, opening a tunable bandgap in Bi-layer graphene by doping the substrate electrically and so on. If an entire device fabrication process can be established which include obtaining graphene samples, attaining all-graphene layers and etching processes using different effective lithographic techniques, then the day is not far away when the “graphene-dream”
